System interconnection power conversion device

ABSTRACT

A voltage drop Vzs is calculated based on an output current detection value Iac and a virtual synchronous impedance Zs or a corrected virtual synchronous impedance Zs′, and a value obtained by subtracting the voltage drop Vzs from an internal induced voltage Ef is output as a grid voltage command value Vac*. Zs calculation unit 7 limits an output current phase θ so that the output current phase θ is within an effective range by a phase limiter 12a, and calculates the corrected virtual synchronous impedance Zs′ based on a limited output current phase θ, the internal induced voltage Ef, a grid voltage detection value Vac and a current limit value Ilim. Accordingly, in grid interconnection power conversion device that controls a virtual synchronous generator, it is possible to continue operation while suppressing an overcurrent and possess a synchronizing power generated by action or working of a virtual synchronous impedance.

TECHNICAL FIELD

The present invention relates to a control method for suppressing anovercurrent caused by a system accident (or a grid accident) etc. in asystem interconnection power conversion device (or a gridinterconnection power conversion device) that controls a virtualsynchronous generator simulating a synchronous generator.

BACKGROUND ART

Non-Patent Document 1 discloses, as a technique for controlling avirtual synchronous generator by a voltage control system, a method forkeeping an output current within a certain constant value by correctinga deviation (a difference) between a voltage command value and a voltagedetection value so that the deviation falls within a certain fixedvalue.

Patent Document 1 discloses a technique for controlling a virtualsynchronous generator by a current control system. Because of thecurrent control system, by limiting a current command value, anovercurrent can be prevented.

In a case of the method of Non-Patent Document 1, since it is notpossible to control a current to a specified current value, an outputcurrent flowing by a main circuit condition (a filter constant, a systemimpedance, etc.) is changed.

In a case of the method of Patent Document 1, if the current commandvalue is limited, a vector that is different from a command value vectorcalculated based on a virtual synchronous impedance model is output.Because of this, a synchronizing power generated by action or working ofthe virtual synchronous impedance cannot be expected.

From the above, in the grid interconnection power conversion device thatcontrols the virtual synchronous generator, a challenge is to continuean operation while suppressing the overcurrent caused by a short circuitaccident etc of the grid and to possess the synchronizing powergenerated by action or working of the virtual synchronous impedance.

CITATION LIST Patent Document

Patent Document 1: Japanese Patent No. 6084863

Patent Document 2: Japanese Patent No. 5830941

Non-Patent Document

Non-Patent Document 1: “Overcurrent control Scheme for VirtualSynchronous Generator” Heisei. 30 (2018), IEEJ (The institute ofElectrical. Engineers of Japan), B section (Power and Energy)

SUMMARY OF THE INVENTION

The present invention was made in view of the above problem andchallenge. As one aspect of the present invention, a gridinterconnection power conversion device interconnecting a DC powersupply through a DC/AC conversion device, an LC filter and a transformerand performing a control of a virtual synchronous generator, the gridinterconnection power conversion device comprises: an internal inducedvoltage calculation unit configured to calculate an internal inducedvoltage on the basis of an output current detection value, an effectivevalue of an AC voltage detection value and a command value of an ACvoltage effective value; a VSG model configured to determine, on thebasis of the internal induced voltage, the output current detectionvalue and a power reference value, an angular frequency simulating asynchronous generator; a Zs compensation unit configured to simulatedrop of a voltage caused by an internal impedance of the synchronousgenerator on the basis of the internal induced voltage, a grid voltagedetection value and the output current detection value and calculate agrid voltage command value; an output voltage control unit configured toperform a voltage control so that the grid voltage detection valuebecomes the grid voltage command value and output a PWM control commandvalue; and a PWM control unit configured to output a gate command of theDC/AC conversion device on the basis of the PWM control command valueand the angular frequency, wherein the Zs compensation unit has a Zscalculation unit configured to calculate an output current phase fromthe output current detection value, limit the output current phase sothat the output current phase is within an effective range by a phaselimiter and calculate a corrected virtual synchronous impedance on thebasis of a limited output current phase, the internal induced voltage,the grid voltage detection value and a current limit value; a Vz_(s)calculation unit configured to calculate a voltage drop on the basis ofa predetermined virtual synchronous impedance and the output currentdetection value in a normal state and calculate the voltage drop on thebasis of the corrected virtual synchronous impedance and the outputcurrent detection value at a time of an occurrence of an overcurrent ;and a subtracter configured to output, as the grid voltage commandvalue, a value obtained by subtracting the voltage drop from theinternal induced voltage.

As one aspect of the present invention, the phase limiter is configuredto calculate a D′-axis that is a midpoint of an upper limit value and alower limit value of the phase limiter, perform a coordinate conversionof the output current phase with the D′-axis being a reference, limitthe output current phase with the D′-axis being the reference, andperform a coordinate conversion of a limited output current phase withan original D-axis being a reference.

As one aspect of the present invention, the phase limiter is configuredto set, as the D′-axis, a phase obtained by subtracting 5Π/4 from theupper limit value of the phase limiter or a phase obtained bysubtracting 3Π/4 from the lower limit value of the phase limiter.

As one aspect of the present invention, the corrected virtualsynchronous impedance is expressed by the following expression (5).

[Expression5] $\begin{matrix}{\begin{bmatrix}r^{\prime} \\x^{\prime}\end{bmatrix} = {{\frac{1}{I_{\lim}}\begin{bmatrix}{\cos\theta} & {\sin\theta} \\{{- \sin}\theta} & {\cos\theta}\end{bmatrix}}\begin{bmatrix}{E_{d} - V_{d}} \\{E_{q} - V_{q}}\end{bmatrix}}} & (5)\end{matrix}$

Where, θ is expressed by the following expression (7).

[Expression7] $\begin{matrix}{{\tan^{- 1}\left( \frac{- \left( {E_{d} - V_{d}} \right)}{E_{q} - V_{q}} \right)} \leq \theta \leq {\tan^{- 1}\left( \frac{E_{q} - V_{q}}{E_{d} - V_{d}} \right)}} & (7)\end{matrix}$

r′, x′: the corrected virtual synchronous impedance

Ilim: the current limit value

θ: the output current phase

Ed: a d-axis component of the internal induced voltage

Eq: a q-axis component of the internal induced voltage

Vd: a d-axis component of the grid voltage detection value

Vq: a q-axis component of the grid voltage detection value

As one aspect of the present invention, the Zs calculation unit isconfigured to set the current limit value as a fixed value, and theVz_(s) calculation unit is configured to, when the output currentdetection value is lower than the current limit value, as the normalstate, calculate the voltage drop on the basis of the virtualsynchronous impedance and the output current detection value, and whenthe output current detection value is the current limit value orgreater, as the time of the occurrence of the overcurrent, calculate thevoltage drop on the basis of the corrected virtual synchronous impedanceand the output current detection value.

As another aspect of the present invention, the Zs calculation unit isconfigured to calculate a magnitude of an output current vector from theoutput current detection value, and set, as the current limit value, avalue limited to a current that can output the magnitude of the outputcurrent vector, and the Vz_(s) calculation unit is configured to comparethe virtual synchronous impedance and the corrected virtual synchronousimpedance, and when the virtual synchronous impedance is greater, as thenormal state, calculate the voltage drop on the basis of the virtualsynchronous impedance and the output current detection value, and whenthe corrected virtual synchronous impedance is greater, as the time ofthe occurrence of the overcurrent, calculate the voltage drop on thebasis of the corrected virtual synchronous impedance and the outputcurrent detection value.

As another aspect of the present invention, the Zs compensation unit hasan overcurrent judgment unit configured to judge whether the normalstate or the time of the occurrence of the overcurrent, the overcurrentjudgment unit has an overcurrent suppressing operation judgment unitconfigured to judge an overcurrent suppressing operation on the basis ofan output current judgment by comparison between a full-waverectification maximum value of the output current detection value and anovercurrent judgment level; an overcurrent returning operation judgmentunit configured to estimate, on the basis of the internal inducedvoltage and the grid voltage detection value, an output currentestimation value when returning from the corrected virtual synchronousimpedance to the virtual synchronous impedance and judge an overcurrentreturning operation on the basis of a first estimation current judgmentby comparison between a square root of sum of squares of the outputcurrent estimation value and a current judgment level; and a latchcircuit configured to, when the overcurrent suppressing operation isjudged by the overcurrent suppressing operation judgment unit, hold anovercurrent suppressing operation state, and when the overcurrentreturning operation is judged by the overcurrent returning operationjudgment unit, hold an overcurrent returning operation state.

As one aspect of the present invention, the overcurrent returningoperation judgment unit is configured to judge the overcurrent returningoperation by an AND condition of a voltage judgment by comparisonbetween a square root of sum of squares of a moving average value of thegrid voltage detection value between power supply cycles and a voltagejudgment level and the first estimation current judgment.

As one aspect of the present invention, the overcurrent suppressingoperation judgment unit is configured to judge the overcurrentsuppressing operation by an OR condition of a second estimation currentjudgment by comparison between the square root of sum of squares of theoutput current estimation value and the overcurrent judgment level andthe output current judgment.

As another aspect of the present invention, a grid interconnection powerconversion device interconnecting a DC power supply through a DC/ACconversion device, an LC filter and a transformer and performing acontrol of a virtual synchronous generator, the grid interconnectionpower conversion device comprises: an internal induced voltagecalculation unit configured to calculate an internal induced voltage onthe basis of an output current detection value, an effective value of anAC voltage detection value and a command value of an AC voltageeffective value; a VSG model configured to determine, on the basis ofthe internal induced voltage, the output current detection value and. apower reference value, an angular frequency simulating a synchronousgenerator; a Zs compensation unit configured to simulate drop of avoltage caused by an internal impedance of the synchronous generator onthe basis of the internal induced voltage, a grid voltage detectionvalue and the output current detection value and calculate a gridvoltage command value; an output voltage control unit configured toperform a voltage control so that the grid voltage detection valuebecomes the grid voltage command value and output a PWM control commandvalue; and a PWM control unit configured to output a gate command of theDC/AC conversion device on the basis of the PWM control command valueand the angular frequency, wherein the Zs compensation unit has a Zscalculation unit configured to calculate an output current phase from anoutput current estimation value, limit the output current phase so thatthe output current phase is within an effective range and calculate acorrected virtual synchronous impedance on the basis of a limited outputcurrent phase , the internal induced voltage, the grid voltage detectionvalue and a current limit value; a Vz_(s) calculation unit configured tocalculate a voltage drop on the basis of the corrected virtualsynchronous impedance and the output current detection value in a normalstate and also at a time of an occurrence of an overcurrent; and asubtracter configured to output, as the grid voltage command value, avalue obtained by subtracting the voltage drop from the internal inducedvoltage.

As one aspect of the present invention, the output current estimationvalue is expressed by the following expression (8).

[Expression8] $\begin{matrix}{\begin{bmatrix}I_{d} \\I_{q}\end{bmatrix} = {{\frac{1}{r^{2} + x^{2}}\begin{bmatrix}r & x \\{- x} & r\end{bmatrix}}\begin{bmatrix}{E_{d} - V_{d}} \\{E_{q} - V_{q}}\end{bmatrix}}} & (8)\end{matrix}$

Id, Iq: the output current estimation value

r, x: virtual synchronous impedance

Ed: a d-axis component of the internal induced voltage

Eq: a q-axis component of the internal induced voltage

Vd: a d-axis component of the grid voltage detection value

Vq: a q-axis component of the grid voltage detection value

According to the present invention, in the grid interconnection powerconversion device that controls the virtual synchronous generator, it ispossible to continue the operation while suppressing the overcurrentcaused by the short circuit accident of the grid etc. and to possess thesynchronizing power generated by action or working of the virtualsynchronous impedance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a drawing showing a virtual impedance model of a systeminterconnection power conversion device (or a grid interconnection powerconversion device).

FIG. 2 is a schematic diagram showing a general configuration of thegrid interconnection power conversion device.

FIG. 3 is a schematic diagram showing a Zs compensation unit ofembodiments 1 to 7.

FIG. 4 is a schematic diagram showing a Zs calculation unit of theembodiments 1 and 2.

FIG. 5 is a schematic diagram showing a phase limiter of the embodiment1.

FIGS. 6A and 6B are vector diagrams with a D-axis and a D′-axis beingreferences.

FIG. 7 is a schematic diagram showing a phase limiter of the embodiment2.

FIG. 8 is a schematic diagram showing a Zs calculation unit of theembodiment 3.

FIG. 9 is a schematic diagram showing a Zs calculation unit of theembodiment 4.

FIG. 10 is a schematic diagram showing an overcurrent judgment unit ofthe embodiment 5.

FIG. 11 is a schematic diagram showing an overcurrent judgment unit ofthe embodiment 6.

FIG. 12 is a schematic diagram showing an overcurrent judgment unit ofthe embodiment 7.

EMBODIMENTS FOR CARRYING OUT THE INVENTION

Embodiments 1 to 7 of a system interconnection power conversion device(or a grid interconnection power conversion device) according to thepresent invention will be described in detail below with reference toFIGS. 1 to 12 .

[Embodiment 1]

FIG. 1 shows a virtual impedance model of a system interconnection powerconversion device (or a grid interconnection power conversion device)used for a PCS (Power Conversion System). As shown in FIG. 1 , the gridinterconnection power conversion device has a DC/AC conversion deviceINV and an LC filter LC (a reactor Lf and a capacitor Cf), and isinterconnected to a system (or a grid) 1.

The grid, interconnection power conversion device performs a voltagecontrol so that a grid voltage detection value Vac after the LC filterLC coincides with a grid voltage command value Vac* obtained bysubtracting a voltage drop, which is caused by the fact that an outputcurrent Iac flows through a virtual synchronous impedance Zs, from aninternal induced voltage Ef.

FIG. 2 is a schematic diagram showing a general configuration of thegrid interconnection power conversion device according to the presentembodiment 1. As shown in FIG. 2 , as a main circuit configuration ofthe grid interconnection power conversion device, a DC power supply Vdcsuch as a storage battery is interconnected to the grid 1 through theDC/AC conversion device INV formed by IGBTs etc., the LC filter LC and atransformer Tr. An output current detection value Iac between the LCfilter LC and the transformer Tr and the grid voltage detection valueVac are detected, and are output to an after-mentioned control block.

The control block of the grid interconnection power conversion deviceaccording to the present embodiment 1 has, as shown in FIG. 2 , aninternal induced voltage calculation unit 2, a VSG model 3, a Zscompensation unit 4, an output voltage control unit 5 and a PWM controlunit 6.

The internal induced voltage calculation unit 2 inputs a command value|Vac|* of an AC voltage effective value, an effective value |Vac| of anAC voltage detection value and the output current detection value Iac,and calculates the internal induced voltage Ef The VSG model 3 inputsthe internal induced voltage Ef, the output current detection value Iacand a power reference value Pm, and determines an angular frequency ωrsimulating a synchronous generator.

The Zs compensation unit 4 inputs the grid voltage detection value Vac,the output current detection value Iac and the internal induced voltageEf, simulates drop of a voltage caused by an internal impedance of thesynchronous generator, and outputs the grid voltage command value Vac*.

The output voltage control unit 5 inputs the grid voltage detectionvalue Vac and the grid voltage command value Vac*, performs a control sothat the grid voltage detection value Vac becomes the grid voltagecommand value Vac*, and outputs a PWM control command value Vcmd. ThePWM control unit 6 inputs the PWM control command value Vcmd and theangular frequency ωr, and outputs a gate command Gate to a switchingelement such as the IGBT of the DC/AC conversion device INV.

Since the internal induced voltage calculation unit 2, the VSG model 3,the output voltage control unit 5 and the PWM control unit 6 are notdirectly related to the present invention, their detailed descriptionsare omitted here.

The Zs compensation unit 4 has, as shown in FIG. 3 , a Zs calculationunit 7, a switch 8, a Vz_(s) calculation unit 9 and a subtracter 10.

The Zs calculation unit 7 calculates a corrected virtual synchronousimpedance Zs′ required to suppress an output current upon occurrence ofan overcurrent. The switch 8 normally outputs a predetermined virtualsynchronous impedance Zs, but outputs the corrected virtual synchronousimpedance Zs′ upon occurrence of the overcurrent. Judgment of the normalstate and the occurrence of the overcurrent is made, for instance, bycomparison between the output current detection value Iac and anovercurrent level (a threshold value).

The Vz_(s) calculation unit 9 calculates a voltage drop Vz_(s) generatedby the output current detection value Iac and the virtual synchronousimpedance Zs or the corrected virtual synchronous impedance Zs′. Thesubtracter 10 subtracts the voltage drop Vz_(s) from the internalinduced voltage Ef, and calculates the grid voltage command value Vac*to be output by the grid interconnection power conversion device.

FIG. 4 is a block diagram showing the Zs calculation unit 7. The Zscalculation unit 7 has a polar coordinate conversion unit 11, a phaselimiter 12 a, a cos unit 13 a, a sin unit 13 b, subtracters 14 a and 14b, multipliers 15 a to 15 d, an adder 16 a, a subtracter 16 b and gainmultipliers 17 a and 17 b.

The polar coordinate conversion unit 11 calculates an output currentphase θ from the output current detection value Iac . The phase limiter12 a limits the output current phase θ so that the output current phaseθ is within an effective range. The cos unit 13 a outputs a cos θ, andthe sin unit 13 b outputs a sin θ.

The subtracter 14 a subtracts a d-axis component Vd of the grid voltagedetection value Vac from a d-axis component Ed of the internal inducedvoltage Ef, and outputs Ed-Vd. The subtracter 14 b subtracts a q-axiscomponent Vq of the grid voltage detection value Vac from a q-axiscomponent Eq of the internal induced voltage Ef, and outputs Eq-Vq.

The multiplier 15 a multiplies the output of the subtracter 14 a by acos θ, and outputs (Ed-Vd) cos θ. The multiplier 15 b multiplies theoutput of the subtracter 14 a by a sin θ, and outputs (Ed-Vd) sin θ. Themultiplier 15 c multiplies the output of the subtracter 14 b by a cos θ,and outputs (Eq-Vq) cos θ. The multiplier 15 d multiplies the output ofthe subtracter 14 b by a sin θ, and outputs (Eq-Vq) sin θ.

The adder 16 a adds the output (Eq-Vq) sin θ of the multiplier 15 d tothe output (Ed-Vd) cos θ of the multiplier 15 a. The subtracter 16 bsubtracts the output (Ed-Vd) sin θ of the multiplier 15 b from theoutput (Eq-Vq) cos θ of the multiplier 15 c.

The gain multiplier 17 a multiplies the output of the adder 16 a by again G (=1/Ilim), and outputs it as r′. The gain multiplier 17 bmultiplies the output of the subtracter 16 b by a gain G (=1/Ilim) , andoutputs it as x′. (r′, x′) becomes the corrected virtual synchronousimpedance Zs′.

The grid interconnection power conversion device performs the voltagecontrol so that the grid voltage detection value Vac after the LC filterLC coincides with the grid voltage command value Vac* obtained bysubtracting the voltage drop, which is caused by the fact that theoutput current Iac flows through the virtual synchronous impedance Zs,from the internal induced voltage Ef.

In the normal state, the virtual synchronous impedance Zs (r and x)according to the synchronous generator to be simulated is set, and thegrid voltage command value Vac* is determined by the set virtualsynchronous impedance Zs.

In a case where, due to a grid accident etc. , the overcurrent occurs inthe grid interconnection power conversion device when the grid voltagecommand value Vac* determined by the virtual synchronous impedance Zshas been output, by switching the virtual synchronous impedance Zs tothe corrected virtual synchronous impedance Zs′ (r′ and x′) required tolimit the output current detection value Iac to a current limit valueIlim which the DC/AC conversion device INV can output, the overcurrentis suppressed.

A calculation method of the corrected virtual synchronous impedance Zs′required to suppress the overcurrent will be described below. From theimpedance model of FIG. 1 , the voltage drop Vz_(s) (=ZsIac) generatedby the virtual synchronous impedance Zs is the following expression (1).

[Expression 1]

Ż_(s)I_({dot over (a)}c)=Ė_(f)−V{dot over (a)}c  (1)

When the expression (1) is treated on DQ coordinates and expressed as adeterminant , the expression (1) becomes the following expression (2).

[Expression2] $\begin{matrix}{{\lbrack\begin{matrix}r \\x\end{matrix}\rbrack} = {{\frac{1}{I_{d}^{2} + I_{q}^{2}}\begin{bmatrix}I_{d} & I_{q} \\{- I_{q}} & I_{d}\end{bmatrix}}\lbrack\begin{matrix}{E_{d} - V_{d}} \\{E_{q} - V_{q}}\end{matrix}\rbrack}} & (2)\end{matrix}$

Here, the virtual synchronous impedance Zs, the output current detectionvalue Iac, the grid voltage detection value Vac and the internal inducedvoltage Ef are expressed. by the following expression (3).

[Expression 3]

Ż_(s)=r+jx

I_(ac)=I_(d)+jI_(q)

{dot over (V)}_(ac)=V_(a)+jV_(q)

Ė_(f)=E_(a)+jE_(q)  (3)

When suppressing the output current, only a magnitude of an outputcurrent vector is limited without changing a phase of the output currentvector. A d-axis component Id and a q-axis component Iq of the outputcurrent detection value Iac after the limitation and the output currentphase e become the following expression (4). Here, Ilim indicates thecurrent limit value, and Id_det/Iq_det indicates d-axis component/q-axiscomponent of the output current detection value.

[Expression4] $\begin{matrix}{{I_{d} - {I_{\lim}\cos\theta}},{I_{q} = {I_{lim}\sin\theta}},{\theta = {\tan^{- 1}\left( \frac{I_{d\_ det}}{I_{q\_ det}} \right)}}} & (4)\end{matrix}$

From the above expressions, the corrected virtual synchronous impedanceZs′ (r′ and x′) required to limit the output current to the currentlimit value him can be determined by the following expression (5).

[Expression5] $\begin{matrix}{\begin{bmatrix}r^{\prime} \\x^{\prime}\end{bmatrix} = {{\frac{1}{I_{\lim}}\begin{bmatrix}{\cos\theta} & {\sin\theta} \\{{- \sin}\theta} & {\cos\theta}\end{bmatrix}}\begin{bmatrix}{E_{d} - V_{d}} \\{E_{q} - V_{q}}\end{bmatrix}}} & (5)\end{matrix}$

FIG. 4 shows the above contents in a block diagram. It is noted that bydefining an internal phase with the internal induced voltage Ef being areference, Eq becomes 0 (Eq=0) and can be simplified.

Next, the phase limiter 12 a will be described. As described above, whencalculating the corrected virtual synchronous impedance Zs′, althoughthe output current phase θ of the output current detection value Iac isused, in order to use it as the virtual impedance model of FIG. 1 , itis necessary to limit the output current phase θ so that the outputcurrent phase θ is within an effective range.

FIG. 5 is a schematic diagram showing the phase limiter 12 a of theembodiment 1. As shown in FIG. 5 , the phase limiter 12 a has a maximumvalue output unit 18 a, a minimum value output unit 18 b, a subtracter19, a multiplier 20, an adder 21, a subtracter 22, subtracters 23 a, 23b and 23 c, a limiter 24 and an adder 25. θ_(IN) indicates a phase inputto the phase limiter 12 a, and θ_(OUT) indicates a phase output from thephase limiter 12 a.

The maximum value output unit 18 a outputs a maximum value of an upperlimit value θ_(H) and a lower limit value θ_(L) of the phase limiter.The minimum value output unit 18 b outputs a minimum value of the upperlimit value θ_(H) and the lower limit value θ_(L) of the phase limiter.The subtracter 19 determines a deviation (a difference) between themaximum value and the minimum value. The multiplier 20 determines aphase that is half of the effective range of the output current phase θby multiplying the deviation by ½.

The adder 21 determines a phase difference from the upper limit valueθ_(H) of the phase limiter to a D′-axis by adding Π to the phase that ishalf of the effective range of the phase θ. The subtracter 22 determinesa phase difference θax from a D-axis to the D′-axis by subtracting theabove phase difference from the upper limit value θ_(H) of the phaselimiter.

The subtracters 23 a, 23 b and 23 c subtract an output of the subtracter22 from the phases θ_(IN), θ_(H) and θ_(L), and convert these phasesθ_(IN), θ_(H) and θ_(L) with the D′-axis being a reference.

The limiter 24 limits an output current phase θ_(IN)′ converted with theD′-axis being the reference by upper and lower limit values θ_(H)′ andθ_(L)′ converted with the D′-axis being the reference. The adder 25 addsan output of the subtracter 22 to an output of the limiter 24, andconverts the limited output current phase with the D-axis being areference. An output of the adder 25 is θ_(OUT.)

FIG. 6A shows a vector diagram with the D-axis being a reference. FIG.6B shows a vector diagram with the D′-axis being a reference. As shownin Fig. 6A, the D′-axis whose phase difference from the lower limitvalue θ_(L) of the limiter is θ_(A) and whose phase difference from theupper limit value θ_(H) of the limiter is θ_(B) is provided. ThisD′-axis is defined in the middle of the upper limit value θ_(H) and thelower limit value θ_(L) of the limiter so that θ_(A) is θ_(B)(θ_(A)=θ_(B)).

A reference point (a point of 0) of the D′-axis is set to a point thatis symmetrical to a midpoint of the upper limit value θ_(H) and thelower limit value θ_(L) of the limiter with a phase being advanced by Π.Each phase is converted with the D-axis being a reference by calculatingthe phase difference θax between this D′-axis and the D-axis from thelower limit value θ_(I), and the upper limit value θ_(H) of the limiter.

By performing the limit process on the basis of phase information withthe D′-axis being the reference, if the vector before the limitation isout of the range, the vector is limited to either one, which is closerto the vector, of the upper limit value θ_(H) or the lower limit valueθ_(L).

More specifically, a vector A is limited to the limiter lower limitvalue θ_(L), while a vector B is limited to the limiter upper limitvalue θ_(H). The phase information after the limitation is convertedinto respective phases with the original D-axis being the reference byadding the phase difference θax.

In the above description, although the D′-axis is calculated with thelimiter upper limit value θ_(H) being a reference, the D′-axis could becalculated with the limiter lower limit value θ_(L) being a reference.

As described above, according to the present embodiment 1, even if theovercurrent occurs in the DC/AC conversion device due to a short circuitaccident etc. of the grid, it is possible to continue an operation withthe current being limited to the current limit value which the DC/ACconversion device can output. Further, since a synchronizing powergenerated by action or working of the virtual synchronous impedance isstill possessed, it is possible to synchronize the device with othervoltage sources even during the current suppression.

In addition, when the output current phase to be limited is out of theeffective range, since the output current phase is limited to eitherone, whose phase difference is smaller, of the upper limit value or thelower limit value of the limiter, a change of the phase by the limiterbecomes small.

[Embodiment 2]

In an embodiment 2, the phase limiter 12 a of the embodiment 1 issimplified. FIG. 7 shows the phase limiter 12 a of the embodiment 2. Asshown in FIG. 7 , the phase limiter 12 a of the present embodiment 2 hasa subtracter 26, a subtracter 27, a limiter 28 and an adder 29.

The subtracter 26 subtracts 5Π/4 from the upper limit value θ_(H) of thephase limiter. The subtracter 27 subtracts an output of the subtracter26 from the phase θ_(IN), and converts the phase θ_(IN) with the D′-axisbeing a reference. The limiter 28 limits the phase em converted with theD′-axis being the reference as 3Π/4≤θ<5Π/4. The adder 29 converts anoutput of the limiter 28 with the D-axis being a reference. An output ofthe adder 29 is the phase θ_(OUT).

In order to simulate the corrected virtual synchronous impedance Zs′,the corrected virtual synchronous impedance Zs′ determined by theexpression (5) must be positive. Although instantaneous output currentphase information is necessary to suppress the overcurrent, if thecorrected virtual synchronous impedance Zs′ is calculated on the basisof phase information extracted from an instantaneous current when theoutput current is disturbed due to a grid accident, a load change andthe like, the corrected virtual synchronous impedance Zs′ may be anegative value. Therefore, the limiter is provided for the extractedoutput current phase θ.

A condition that the corrected virtual synchronous impedance r′ and x′become positive values from an equation of the corrected virtualsynchronous impedance Zs′ of the expression (5) is the followingexpression (6).

[Expression6] $\begin{matrix}\left\{ \begin{matrix}{{{\left( {E_{d} - V_{d}} \right)\cos\theta} + {\left( {E_{q} - V_{q}} \right)\sin\theta}} \geq 0} \\{{{{- \left( {E_{d} - V_{d}} \right)}\sin\theta} + {\left( {E_{q} - V_{q}} \right)\cos\theta}} \geq 0}\end{matrix} \right. & (6)\end{matrix}$

From the expression (6) , the output current phase θ needs to be limitedto within a range of the following expression (7).

[Expression7] $\begin{matrix}{{\tan^{- 1}\left( \frac{- \left( {E_{d} - V_{d}} \right)}{E_{q} - V_{q}} \right)} \leq \theta \leq {\tan^{- 1}\left( \frac{E_{q} - V_{q}}{E_{d} - V_{d}} \right)}} & (7)\end{matrix}$

Since denominator and numerator of the upper limit value and the lowerlimit value are opposite in the expression (7), a deviation (adifference) between the upper limit value and the lower limit value isfixed at Π/2. Therefore, because of θ_(A)=θ_(B)=Π/4, a phase differencefrom the upper limit value ex to the D′-axis becomes 5Π/4. Here,although a method for calculating the D′-axis with the upper limit valueθ_(H) being a reference has been described, the D′-axis could becalculated with the lower limit value θ_(I), being a reference. In thecase where the lower limit value θ_(L), is the reference, the phasedifference becomes 3Π/4.

From the above, a configuration of the phase limiter (FIG. 5 ) of theembodiment I can be simplified as shown in FIG. 7 .

As described above, the present embodiment 2 can obtain the same workingand effect as those of the embodiment 1. Further, the phase limiter canbe configured with a simpler configuration than that of the embodiment1.

[Embodiment 3]

An embodiment 3 is the same as the embodiments 1 and 2 except for the Zscalculation unit 7. FIG. 8 shows the Zs calculation unit 7 of thepresent embodiment 3. Different points from the embodiments 1 and 2 willbe described below.

In the embodiments 1 and 2 , the current limit value Ilim is a fixedvalue. However, in the present embodiment 3, a current limiter 12 b forlimiting a magnitude (an amplitude a) of the output current detectionvalue Iac is provided. Further, instead of the gain multipliers 17 a and17 b, dividers 30 a and 30 b are provided, and divide outputs of theadder 16 a and the subtracter 16 b by a limited output current detectionvalue output from the current limiter 12 b.

In the embodiments 1 and 2, the predetermined virtual synchronousimpedance Zs and the corrected virtual synchronous impedance Zs′calculated by the Zs calculation unit 7 are switched by the detection ofthe overcurrent.

In contrast to this, in the present embodiment 3, as the current limitvalue Ilim, a value obtained by limiting the magnitude (the amplitude a)of the output current detection value Iac by the overcurrent level isused. Then, the switch 8 in FIG. 3 compares the predetermined virtualsynchronous impedance Zs and the corrected virtual synchronous impedanceZs′ calculated by the Zs calculation unit 7, and selects the virtualsynchronous impedance having a greater impedance value.

As described above, according to the present embodiment 3, the sameworking and effect as those of the embodiments 1 and 2 are obtained.Further, since an amount of change between the virtual synchronousimpedance Zs and the corrected virtual synchronous impedance Zs′ becomessmall when the virtual synchronous impedance is switched, a currentchange during the overcurrent suppression operation becomes gentle, thenan overshoot can be suppressed. Furthermore, since the judgment of theovercurrent becomes unnecessary, the circuit configuration issimplified, and adjustment of the current limit value is unnecessary.

[Embodiment 4]

When the above expression (1) is solved for the current, the followingexpression (8) is obtained.

[Expression8] $\begin{matrix}{\begin{bmatrix}I_{d} \\I_{q}\end{bmatrix} = {{\frac{1}{r^{2} + x^{2}}\begin{bmatrix}r & x \\{- x} & r\end{bmatrix}}\begin{bmatrix}{E_{d} - V_{d}} \\{E_{q} - V_{q}}\end{bmatrix}}} & (8)\end{matrix}$

From the expression (8), the current flowing when the set virtualsynchronous impedance Zs is simulated can be estimated.

The output current detection value Iac used in the configurations of theembodiments 1 to 3 is replaced with output current estimation values Idand Iq calculated by the expression (8), and these values are used.

FIG. 9 shows the Zs calculation unit 7 of an embodiment 4. Differentpoints from the embodiment 3 will be described below.

A multiplier 31 a multiplies the output (Ed-Vd) of the subtracter 14 aby r/r²+x². A multiplier 31 b multiplies the output (Eq-Vq) of thesubtracter 14 b by x/r²+x². A multiplier 31 c multiplies the output(Eq-Vq) of the subtracter 14 b by r/r²+x². A multiplier 31 d multipliesthe output (Ed-Vd) of the subtracter 14 a by x/r²+x².

An adder 32 a adds an output of the multiplier 31 b to an output of themultiplier 31 a. A subtracter 32 b subtracts an output of the multiplier31 d from an output of the multiplier 31 c. Outputs of the adder 32 aand the subtracter 32 b are the output current estimation values Id andlq respectively. In the present embodiment 4, these output currentestimation values Id and Iq are output to the polar coordinateconversion unit 11.

When calculating the corrected virtual synchronous impedance on thebasis of the output current estimation values Id and Iq, in the normalstate (there is no limitation by the limiter of the current amplitude orthe phase), r′ and x′ are equivalent to the preset r and x.

On the other hand, at the time of the overcurrent, since the currentamplitude is limited, the corrected virtual synchronous impedance Zs′(r′ and x′) required to suppress the output current is calculated.Therefore, in the present embodiment 4, the switch 8 of FIG. 3 becomesunnecessary.

Therefore, according to the present embodiment 4, in addition to theworking and effect of the embodiments 1 to 3, a switching operation ofthe virtual synchronous impedance according to the presence or absenceof the occurrence of the overcurrent can be eliminated.

[Embodiment 5]

In an embodiment 5, an overcurrent judgment unit that judges whether thegrid interconnection power conversion device is in the normal state orthe overcurrent occurs will be described. FIG. 10 is a schematic diagramshowing the overcurrent judgment unit of the present embodiment 5. Asshown in FIG. 10 , the overcurrent judgment unit has an overcurrentsuppressing operation judgment unit 33, an overcurrent returningoperation judgment unit 34 and a latch circuit 35.

The overcurrent suppressing operation judgment unit 33 has a maximumcurrent judgment unit 36 and a comparator 37. The maximum currentjudgment unit 36 determines an output current maximum value of afull-wave rectification value from three phase instantaneous values ofthe output current detection value Iac. Here, it could also be possibleto use an absolute value of a current vector by square root of sum ofsquares from two phase signals after DQ conversion. The comparator 37performs an output current judgment by comparison between the outputcurrent maximum value and an overcurrent judgment level OC_Level, andoutputs a signal of “1” level when the output current maximum value isgreater.

The overcurrent returning operation judgment unit 34 has an outputcurrent estimation unit 38, an RSS (Root Sum Square) 39 and a comparator40. The output current estimation unit 38 estimates, on the basis of theinternal induced voltage Ef and the grid voltage detection value Vac, anoutput current estimation value flowing when returning the virtualsynchronous impedance from the corrected virtual synchronous impedanceZs′ to the virtual synchronous impedance Zs. The RSS 39 determines anabsolute value of a vector of the estimated output current estimationvalue. The comparator 40 performs a first estimation current judgment bycomparison between the absolute value of the vector of the outputcurrent estimation value and a current judgment level I_Level, andoutputs a signal of “1” level when the absolute value of the vector ofthe output current estimation value is smaller.

The latch circuit 35 sets the overcurrent suppressing operation andholds an overcurrent suppressing operation state when an output of theovercurrent suppressing operation judgment unit 33 is the “1” levelsignal, and clears the overcurrent suppressing operation and holds anovercurrent returning state when an output of the overcurrent returningoperation judgment unit 34 is the “1” level signal. That is, when theovercurrent is judged by or in the overcurrent suppressing operationjudgment unit 33, the overcurrent suppressing operation state is held,while when the overcurrent returning operation is judged by or in theovercurrent returning operation judgment unit 34, the overcurrentreturning state is held.

A switch judgment operation of the virtual synchronous impedance will bedescribed below. When the maximum value of the full-wave rectificationis calculated from the three phase instantaneous values of the outputcurrent detection value Iac and the maximum value exceeds theovercurrent judgment level OC_Level, the overcurrent is judged. When theovercurrent is judged, the virtual synchronous impedance Zs is switchedto the corrected virtual synchronous impedance Zs′ for suppressing theovercurrent. A judgment signal of the overcurrent suppressing operationis held in the latch circuit 35. Here, for the overcurrent suppressingoperation judgment, square root of sum of squares can be used fromDQ-axis components of the output current.

A returning condition judgment from the overcurrent suppressingoperation uses the output current estimation value. From the expression(8), the output current output when returning the virtual synchronousimpedance from the corrected virtual synchronous impedance Zs′ to thevirtual synchronous impedance Zs can be estimated. By calculating theabsolute value of the output current vector (square root of sum ofsquares of the output current vectors) estimated by the expression (8)and comparing it with the current judgment level I_Level, a judgment ismade as to whether or not the overcurrent occurs when returning thevirtual synchronous impedance from the corrected virtual synchronousimpedance Zs′ to the virtual synchronous impedance Zs.

When the returning from an overcurrent state is judged, the switch 8switches from the corrected virtual synchronous impedance Zs′ to thevirtual synchronous impedance Zs. A judgment signal of the overcurrentreturning operation is held in the latch circuit 35.

As described above, according to the present embodiment 5, even if theovercurrent occurs in the DC/AC conversion device due to a short circuitaccident etc. of the grid, it is possible to continue an operation withthe current being limited to the current limit value which the DC/ACconversion device can output. Further, since a synchronizing powergenerated by action or working of the virtual synchronous impedance isstill possessed, it is possible to synchronize the device with othervoltage sources even during the current suppression.

In addition, by performing the overcurrent returning operation judgmentfrom the estimated current, a situation where the overcurrent stateoccurs again when returning the virtual synchronous impedance from thecorrected virtual synchronous impedance Zs′ to the virtual synchronousimpedance Zs then the overcurrent suppressing operation and the normaloperation are repeated can be suppressed, thereby stably switchingbetween the overcurrent suppressing operation and the normal operation.

[Embodiment 6]

An embodiment 6 is the same as the embodiment 5 except for theovercurrent returning operation judgment unit 34 of the overcurrentjudgment unit. FIG. 11 shows the overcurrent judgment unit of thepresent embodiment 6. In the present embodiment 6, as shown in FIG. 11 ,a moving average unit 41, an RSS 42, a comparator 43 and a logicalproduct unit (or an AND unit) 44 are added to the overcurrent returningoperation judgment unit 34 of the embodiment 5.

The moving average unit 41 performs a moving average process of the gridvoltage detection value Vac between power supply cycles. The RSS 42determines an absolute value of the moving average grid voltagedetection value. The comparator 43 performs a voltage judgment bycomparison between a voltage judgment level V_Level and an output (theabsolute value of the moving average grid voltage detection value Vac)of the RSS 42, and outputs a signal of “1” level when the output of theRSS 42 is greater. The AND unit 44 outputs a signal of “1” level whenoutputs of the comparators 40 and 43 are both “1” level signals, andoutputs a signal of “0” level in the other cases. That is, theovercurrent returning operation is judged by an AND condition of thefirst estimation current judgment and the voltage judgment.

The present embodiment 6 is the embodiment in which the judgmentcondition by the grid voltage is added to the overcurrent returningoperation judgment unit 34 of the embodiment 5.

If a two-phase short circuit accident occurs on the grid 1 side, thegrid voltage is brought into an imbalance state. Since the gridinterconnection power conversion device operates as a voltage sourcewith. three-phase equilibrium, the output current oscillates andperiodically exceeds the overcurrent level. In order to avoid therepetition of the overcurrent suppressing operation and the normaloperation when the two-phase short circuit occurs, the voltage judgmentby the grid voltage is provided.

If the DQ coordinate conversion is performed for a three-phase imbalancevoltage (a voltage with three-phase imbalance), pulsation of the powersupply cycle occurs in each of the D-axis and the Q-axis. Therefore, byperforming the moving average process between power supply cycles, thispulsation is removed. As a method of the moving average process, thereare a method in which sampling is performed in synchronization with thepower supply cycle and a method in which sampling is performedasynchronously with the power supply cycle.

Although either method is possible, since an internal angular frequencyand a grid frequency do not necessarily coincide with each other at anoccurrence of grid disturbance etc. in the virtual synchronous generatorcontrol, the method in which the sampling is performed asynchronously,such as Patent Document 2, is desirable.

By the above method, by calculating the absolute value of the vector(square root of sum of squares of the vectors) of the grid voltagedetection value Vac from which the pulsation component is removed andcomparing it with the voltage judgment level V Level, a judgment is madeas to whether returning from a short circuit state occurs or not.

When the AND condition of the first estimation current judgment and thevoltage judgment is satisfied, the virtual synchronous impedance isswitched from the corrected virtual synchronous impedance Zs′ to thevirtual synchronous impedance Zs. A judgment signal of the overcurrentreturning operation is held in the latch circuit 35.

As described above, the present embodiment 6 can obtain the same workingand effect as those of the embodiment 5. Further, even in the case wherethe two-phase short circuit accident occurs, it is possible to continuethe overcurrent suppressing operation without repeating the overcurrentsuppressing operation and the normal operation during the short circuit,and a stable current can be output.

[Embodiment 7]

An embodiment 7 is the same as the embodiment 6 except for theovercurrent suppressing operation judgment unit 33 of the overcurrentjudgment unit. FIG. 12 shows the overcurrent judgment unit of thepresent embodiment 7. In the present embodiment 7, as shown in FIG. 12 ,a comparator 45 and a logical sum unit (or an OR unit) 46 are added tothe overcurrent suppressing operation judgment unit 33 of the embodiment6.

The comparator 45 performs a second estimation current judgment bycomparison between the absolute value (the output of the RSS 39) of thevector of the output current estimation value estimated by the outputcurrent estimation unit 38 in the overcurrent returning operationjudgment unit 34 and the overcurrent judgment level OC_Level, andoutputs a signal of “1” level when the output of the RSS 39 is greater.The OR unit 46 outputs a signal of “1” level when at least one of theoutputs of the comparators 37 and 45 is “1” level signal, and outputs asignal of “0” level when both of the outputs of the comparators 37 and45 are “0” level signal. That is, the overcurrent suppressing operationis judged by an OR condition of the output current judgment and thesecond estimation current judgment.

The present embodiment 7 is the embodiment in which the secondestimation current judgment is added to the overcurrent suppressingoperation judgment unit 33 of the embodiments 5 and 6. When the ORcondition of the added second estimation current judgment and the outputcurrent judgment is satisfied, the overcurrent suppressing operation isjudged.

Upon the occurrence of the short circuit accident of the grid, by thefact that drop of the grid voltage occurs, a voltage difference betweenan output voltage of the grid interconnection power conversion deviceand the grid voltage occurs, then the output current increases. By usingthe estimated current, the overcurrent state can be judged before anactual output current increases.

As described above, according to the present embodiment 7, the sameworking and effect as those of the embodiments 5 and 6 are obtained.Further, since it is possible to quickly shift to the overcurrentsuppressing operation when the short circuit accident of the gridoccurs, even in a case where an impedance up to a short circuit point ofthe grid is small and the output current abruptly or sharply increases,the overcurrent can be suppressed. Although FIG. 12 shows a drawing inwhich the present embodiment 7 is applied to the embodiment 6, thepresent embodiment 7 could be applied to the embodiment 5.

Only the above embodiments have been described in detail in the presentinvention. However, it is obvious to a person having ordinary skill inthe art that variety of modifications and changes are possible withinthe scope of technical ideas of the present invention. As a matter ofcourse, such modifications and changes belong to the scope of claim forpatent.

1. A grid interconnection power conversion device interconnecting a DC power supply through a DC/AC conversion device, an LC filter and a transformer and performing a control of a virtual synchronous generator, the grid interconnection power conversion device comprising: an internal induced voltage calculation unit configured to calculate an internal induced voltage on the basis of an output current detection value, an effective value of an AC voltage detection value and a command value of an AC voltage effective value; a VSG model configured to determine, on the basis of the internal induced voltage, the output current detection value and a power reference value, an angular frequency simulating a synchronous generator; a Zs compensation unit configured to simulate drop of a voltage caused by an internal impedance of the synchronous generator on the basis of the internal induced voltage, a grid voltage detection value and the output current detection value and calculate a grid voltage command value; an output voltage control unit configured to perform a voltage control so that the grid voltage detection value becomes the grid voltage command value and output a PWM control command value; and a PWM control unit configured to output a gate command of the DC/AC conversion device on the basis of the PWM control command value and the angular frequency, wherein the Zs compensation unit has a Zs calculation unit configured to calculate an output current phase from the output current detection value, limit the output current phase so that the output current phase is within an effective range by a phase limiter and calculate a corrected virtual synchronous impedance on the basis of a limited output current phase, the internal induced voltage, the grid voltage detection value and a current limit value; a Vz_(s) calculation unit configured to calculate a voltage drop on the basis of a predetermined virtual synchronous impedance and the output current detection value in a normal state and calculate the voltage drop on the basis of the corrected virtual synchronous impedance and the output current detection value at a time of an occurrence of an overcurrent; and a subtracter configured to output, as the grid voltage command value, a value obtained by subtracting the voltage drop from the internal induced voltage.
 2. The grid interconnection power conversion device as claimed in claim 1, wherein the phase limiter is configured to calculate a D′-axis that is a midpoint of an upper limit value and a lower limit value of the phase limiter, perform a coordinate conversion of the output current phase with the D′-axis being a reference, limit the output current phase with the D′-axis being the reference, and perform a coordinate conversion of a limited output current phase with an original D-axis being a reference.
 3. The grid interconnection power conversion device as claimed in claim 2, wherein the phase limiter is configured to set, as the D′-axis, a phase obtained by subtracting 5π/4 from the upper limit value of the phase limiter or a phase obtained by subtracting 3π/4 from the lower limit value of the phase limiter.
 4. The grid interconnection power conversion device as claimed in claim 1, wherein the corrected virtual synchronous impedance is expressed by the following expression (5), [Expression5] $\begin{matrix} {\begin{bmatrix} r^{\prime} \\ x^{\prime} \end{bmatrix} = {{\frac{1}{I_{\lim}}\begin{bmatrix} {\cos\theta} & {\sin\theta} \\ {{- \sin}\theta} & {\cos\theta} \end{bmatrix}}\begin{bmatrix} {E_{d} - V_{d}} \\ {E_{q} - V_{q}} \end{bmatrix}}} & (5) \end{matrix}$ where θ is expressed by the following expression (7), [Expression7] $\begin{matrix} {{\tan^{- 1}\left( \frac{- \left( {E_{d} - V_{d}} \right)}{E_{q} - V_{q}} \right)} \leq \theta \leq {\tan^{- 1}\left( \frac{E_{q} - V_{q}}{E_{d} - V_{d}} \right)}} & (7) \end{matrix}$ where r′, x′: the corrected virtual synchronous impedance Ilim: the current limit value θ: the output current phase Ed: a d-axis component of the internal induced voltage Eq: a q-axis component of the internal induced voltage Vd: a d-axis component of the grid voltage detection value Vq: a q-axis component of the grid voltage detection value.
 5. The grid interconnection power conversion device as claimed in claim 1, wherein the Zs calculation unit is configured to set the current limit value as a fixed value, and the Vz_(s) calculation unit is configured to, when the output current detection value is lower than the current limit value, as the normal state, calculate the voltage drop on the basis of the virtual synchronous impedance and the output current detection value, and when the output current detection value is the current limit value or greater, as the time of the occurrence of the overcurrent, calculate the voltage drop on the basis of the corrected virtual synchronous impedance and the output current detection value.
 6. The grid interconnection power conversion device as claimed in claim 1, wherein the Zs calculation unit is configured to calculate a magnitude of an output current vector from the output current detection value, and set, as the current limit value, a value limited to a current that can output the magnitude of the output current vector, and the Vz_(s) calculation unit is configured to compare the virtual synchronous impedance and the corrected virtual synchronous impedance, and when the virtual synchronous impedance is greater, as the normal state, calculate the voltage drop on the basis of the virtual synchronous impedance and the output current detection value, and when the corrected virtual synchronous impedance is greater, as the time of the occurrence of the overcurrent, calculate the voltage drop on the basis of the corrected virtual synchronous impedance and the output current detection value.
 7. The grid interconnection power conversion device as claimed in claim 1, wherein the Zs compensation unit has an overcurrent judgment unit configured to judge whether the normal state or the time of the occurrence of the overcurrent, the overcurrent judgment unit has an overcurrent suppressing operation judgment unit configured to judge an overcurrent suppressing operation on the basis of an output current judgment by comparison between a full-wave rectification maximum value of the output current detection value and an overcurrent judgment level; an overcurrent returning operation judgment unit configured to estimate, on the basis of the internal induced voltage and the grid voltage detection value, an output current estimation value when returning from the corrected virtual synchronous impedance to the virtual synchronous impedance and judge an overcurrent returning operation on the basis of a first estimation current judgment by comparison between a square root of sum of squares of the output current estimation value and a current judgment level; and a latch circuit configured to, when the overcurrent suppressing operation is judged by the overcurrent suppressing operation judgment unit, hold an overcurrent suppressing operation state, and when the overcurrent returning operation is judged by the overcurrent returning operation judgment unit, hold an overcurrent returning operation state.
 8. The grid interconnection power conversion device as claimed in claim 7, wherein the overcurrent returning operation judgment unit is configured to judge the overcurrent returning operation by an AND condition of a voltage judgment by comparison between a square root of sum of squares of a moving average value of the grid voltage detection value between power supply cycles and a voltage judgment level and the first estimation current judgment.
 9. The grid interconnection power conversion device as claimed in claim 7, wherein the overcurrent suppressing operation judgment unit is configured to judge the overcurrent suppressing operation by an OR condition of a second estimation current judgment by comparison between the square root of sum of squares of the output current estimation value and the overcurrent judgment level and the output current judgment.
 10. A grid interconnection power conversion device interconnecting a DC power supply through a DC/AC conversion device, an LC filter and a transformer and performing a control of a virtual synchronous generator, the grid interconnection power conversion device comprising: an internal induced voltage calculation unit configured to calculate an internal induced voltage on the basis of an output current detection value, an effective value of an AC voltage detection value and a command value of an AC voltage effective value; a VSG model configured to determine, on the basis of the internal induced voltage, the output current detection value and a power reference value, an angular frequency simulating a synchronous generator; a Zs compensation unit configured to simulate drop of a voltage caused by an internal impedance of the synchronous generator on the basis of the internal induced voltage, a grid voltage detection value and the output current detection value and calculate a grid voltage command value; an output voltage control unit configured to perform a voltage control so that the grid voltage detection value becomes the grid voltage command value and output a PWM control command value; and a PWM control unit configured to output a gate command of the DC/AC conversion device on the basis of the PWM control command value and the angular frequency, wherein the Zs compensation unit has a Zs calculation unit configured to calculate an output current phase from an output current estimation value, limit the output current phase so that the output current phase is within an effective range and calculate a corrected virtual synchronous impedance on the basis of a limited output current phase, the internal induced voltage, the grid voltage detection value and a current limit value; a Vz_(s) calculation unit configured to calculate a voltage drop on the basis of the corrected virtual synchronous impedance and the output current detection value in a normal state and also at a time of an occurrence of an overcurrent; and a subtracter configured to output, as the grid voltage command value, a value obtained by subtracting the voltage drop from the internal induced voltage.
 11. The grid interconnection power conversion device as claimed in claim 10, wherein the output current estimation value is expressed by the following expression (8), [Expression8] $\begin{matrix} {\begin{bmatrix} I_{d} \\ I_{q} \end{bmatrix} = {{\frac{1}{r^{2} + x^{2}}\begin{bmatrix} r & x \\ {- x} & r \end{bmatrix}}\begin{bmatrix} {E_{d} - V_{d}} \\ {E_{q} - V_{q}} \end{bmatrix}}} & (8) \end{matrix}$ where Id, Iq: the output current estimation value r, x: virtual synchronous impedance Ed: a d-axis component of the internal induced voltage Eq: a q-axis component of the internal induced voltage Vd: a d-axis component of the grid voltage detection value Vq: a q-axis component of the grid voltage detection value. 